DK-DSP-3C120N【PDF 4/92 页】KIT DEV DSP CYCLONE III EDITION

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20 nm Device Portfolio

Arria 10 GX FPGA Features

www.altera.com/selector

The following features, packages, and I/O matrices give you an overview of our devices. To get more details about these

devices or other older devices that are available, check out our online selector guide at www.altera.com/selector .

Arria ? 10 GX FPGAs: Up to 96 full-duplex transceivers with data rates up to 17.4 Gbps, 16 Gbps backplane, and up to 1,150K

equivalent logic elements (LEs).

Maximum Resource Count for Arria 10 GX FPGAs 1

10AX016

10AX022

10AX027

10AX032

10AX048

10AX057

10AX066

10AX090

10AX115

Adaptive logic modules

(ALMs)

LEs (K)

Registers

M20K memory blocks

M20K memory (Mb)

MLAB memory (Mb)

61,510

160

246,040

440

9

1

83,730

220

334,920

588

11

1.8

101,620

270

406,480

750

15

2.4

118,730

320

474,920

891

17

2.8

181,790

480

727,160

1,438

28

4.3

217,080

570

868,320

1,800

35

5.0

250,540

660

1,002,160

2,133

42

5.7

339,620

900

1,358,480

2,423

47

9.2

427,200

1,150

1,708,800

2,713

53

12.7

Variable-precision digital

signal processing (DSP)

156

192

800

985

1,368

1,612

1,855

1,518

1,518

blocks

18 x 19 multipliers

312

382

1,660

1,970

2,736

3,046

3,356

3,036

3,036

Global clock networks

32

Regional clock networks

8

8

8

8

8

8

16

16

16

Design security

I/O voltage levels

supported (V)

I/O standards supported

Bitstream encryption with authentication

1.2, 1.25, 1.35, 1.8, 2.5, 3.0 2

3 V I/Os Only: 3 V LVTTL, 2.5 V CMOS

DDR and LVDS I/Os: POD12, POD10, Differential POD12, Differential POD10, LVDS, RSDS, mini-LVDS, LVPECL

All I/Os: 1.8 V CMOS, 1.5 V CMOS, 1.2 V CMOS, SSTL-18 (I and II), SSTL-15 (I and II), SSTL-135, SSTL-125,

SSTL-12, HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II), HSUL-12, Differential SSTL-18 (I and II),

Differential SSTL-15 (I and II), Differential SSTL-135, Differential SSTL-125, Differential SSTL-12,

Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12

LVDS channels, 1.6 Gbps

(receive/transmit)

120

120

168

168

222

324

324

384

384

Embedded dynamic phase

alignment (DPA) circuitry

On-chip termination (OCT)

3

Series, parallel, and differential

PCI Express (PCIe )

Transceivercount

? ?

hard IP blocks (Gen3)

12

1

12

1

24

2

24

2

36

2

48

2

48

2

96

4

96

4

Memory devices supported

DDR4, DDR3, DDR2, QDR IV, QDR II+, QDR II+ Xtreme, LPDDR3, LPDDR2, RLDRAM 3, RLDRAM II, LLDRAM II, HMC

1

2

All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.altera.com .

3.0 V compliant, requires a 3 V power supply.

2

Altera Product Catalog

?

2013

?

www.altera.com

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